Method for producing a semiconductor component comprising a t-shaped contact electrode

ABSTRACT

In order to fabricate a semiconductor component having a contact electrode that is T-shaped in cross section, in particular a field-effect transistor with a T gate, a method is described in which a self-aligning positioning of gate base and gate head is effected by means of a spacer produced on a material edge.

CROSS REFERENCE TO RELATED APPLICATIONS

Applicants claim priority under 35 U.S.C. §119 of GERMAN Application No.101 01 825.8 filed on 17 Jan. 2001. Applicants also claim priority under35 U.S.C. §365 of PCT/EP02/00264 filed on Jan. 14, 2002. Theinternational application under PCT article 21(2) was not published inEnglish.

DESCRIPTION

The invention relates to a method for fabricating a semiconductorcomponent having a metallic contact electrode that is T-shaped in crosssection, in particular a field-effect transistor with a T-shaped metalgate.

In field-effect transistors, the gate length is a dimension thatcritically determines the limiting frequency of the transistor, so thatthe shortest possible gate length is sought for high frequencies. On theother hand, the lead resistance of the gate electrode is also intendedto be as low as possible. The features of short gate length and low leadresistance can be realized in particular by means of metallic gateelectrodes with a narrow gate base and a wide gate head by comparisontherewith, so-called T-shaped electrodes (T gate).

Very small gate lengths in the submicron range, in particular less than0.2 μm, can currently be fabricated only with limited reliability usingdirect optical lithography.

DE 39 11 512 A1 discloses a self-aligning method for fabricating acontrol electrode in which openings for structures of source and drainelectrodes are produced photolithographically in a resist layer. Bymeans of undercutting, the region between the source and drainstructures is intended to be reduced to a narrow dummy gate which, in alater method stage, surrounded by a new resist layer, centers theetching of a gate head structure and is removed before the deposition ofthe gate metal. However, in reality the undercutting leads to a dummygate form having a widened base. The undercutting is not reproduciblewith sufficient precision. In addition, the distance between theopenings for the structures of source and drain electrodes cannot be setsufficiently accurately as an initial basis for the width of the dummygate during the direct optical lithography.

The technique of defining a lateral structure in the submicron range bymeans of a layer, deposited on a vertical step sidewall, as auxiliarylayer having a thickness that can be set accurately has long been knownper se. By way of example, IEEE Electron Device Letters, EDL-2, No 1,January 1981, pp. 4-6 by Hunter et al., A New Edge-Defined Approach forSubmicrometer MOSFET Fabrication, describes a method in which twoelements with lateral submicron dimensions produced with respect to thesidewalls of a step structure serve, after the removal of the stepstructure, as masks for producing very narrow gate structures inunderlying layers. Such elements produced on vertical sidewalls are alsoreferred to as side spacers or hereinafter also simply as spacers.

DE 195 48 058 C2 describes a method for fabricating a MOS transistor inwhich spacers are produced on spaced-apart sidewalls of a structureproduced photolithographically, which spacers serve as a mask for asubsequent etching of an underlying conductive first electrode layer, sothat material webs remain as gate base below the spacers. A secondelectrode layer deposited thereabove over the whole area is patternedphotolithographically in order to produce a gate head.

In EP 0 240 683, the gate length of a GaAs JFET is defined by an SiNspacer on a vertical edge of a photoresist structure. After aplanarization of the SiN spacer, the latter masks the etching of thehighly doped cap layer and thus defines the gate of the JFET.

A corresponding procedure is disclosed in U.S. Pat. No. 5,202,272 forfabricating a FET using silicon technology.

JP 04-196 135 A shows a method for fabricating a T gate with a shortgate ength by producing an SiO₂ spacer on a vertical edge of aphotoresist mask deposited above a semiconductor substrate, which spacerserves as a dummy for the gate base in a ate base layer and is removedagain. In a head layer deposited thereabove, an opening as structure forthe gate head is produced using a separate mask. In a uniform depositionstep, the gate metal for forming the T-shaped gate is deposited into thegap of the dummy gate and the opening in the head layer. In anintermediate step, the spacer on the vertical edge of the photoresistmask may also serve for the self-aligning production of a low-impedancesource region.

In a method disclosed in JP 02-208 945, a spacer is likewise produced ona vertical edge a a dummy gate and is subsequently removed withadditional etching of a recess trench before a further photoresist layeris deposited and, in the latter, an opening for the structure of thegate head is produced above the gap of the dummy gate by means of aseparate mask. Gate metal for forming a T-shaped gate is deposited intothe opening of the further photoresist layer and into the gap of thedummy gate and excess metal on the further photoresist layer is removedby lift-off.

U.S. Pat. No. 5,391,510 describes a method in which a dummy gate isproduced by means of a spacer on a vertical layer edge, which dummy gateis surrounded by an insulator layer and is removed to leave a gap whichforms the structure for the gate base. The T-shaped gate is completed bywhole-area deposition of a gate metal layer and subsequent etching.

EP 0 177 129 discloses a method in which the gate is defined directly bya metallic spacer, but without the possibility of producing a wider gatehead.

EP 0 591 608 A2 describes a first fabrication method, which combinesoptical lithography for the gate head and electron beam lithography forthe gate base by means of two different photoresist layers deposited oneabove the other. However, electron beam lithography is an expensive andtime-consuming step in production with an unsatisfactory yield.

Therefore, the same document proposes a new method, in which aninsulator layer is deposited onto the semiconductor material and avertical step is produced in said insulator layer by means of opticallithography. A metal layer deposited over the area is also deposited onthe vertical step sidewall. After planarization and production of a gatehead mask above the vertical step, it is possible to remove the metallayer on the step sidewall. The resulting gap serves as a mask for theetching of a recess trench and for the deposition of the gate basemetal. The layer thickness of the metal layer deposited on the stepsidewall can be set very accurately according to known methods, so thata very short gate length can be realized in a reliable manner. However,the risk of misalignment between gate base and gate head arises as aresult of the separate lithography steps for the vertical step, on theone hand, and the gate head mask.

The known method comprises further disadvantageous steps, in particular,in the advanced stage of fabrication, etching processes with an openrecess trench and/or partly uncovered semiconductor contact layers,which can adversely affect the properties of the component.

In a method disclosed in U.S. Pat. No. 5,399,896, firstly a recesstrench is defined with a first spacer (outside spacer) on a stepsidewall and by means of an Al implantation and, on the resultingsidewalls of the recess trench, further spacer layers (inside spacer)are produced in a manner facing one another, whose lateral spacingdetermines the gate length and is filled with gate metal. The gatelength actually produced depends on the lateral dimensions of the firstand of the further spacers, which are in turn influenced by the heightsof the respective vertical steps. Poor reproducibility of the gatelength is expected due to the multiplicity of parameters influencing thegate length. What is disadvantageous about the method, moreover, is thatthe recess bottom can be damaged during the second spacer etching, whichcan lead to an impairment of the component properties.

The invention is based on the object of specifying an advantageousmethod for fabricating a T-shaped electrode with a very narrow electrodebase.

The invention is described in patent claim 1. The dependent claimscontain advantageous refinements and developments of the invention. Theinvention is described below on the basis of the preferred use for thefabrication of a gate electrode of a field-effect transistor aselectrode of a semiconductor component, but without being restrictedthereto.

The invention makes use of the technique—known per se and describedextensively in the introduction—for producing very fine lateralstructures by means of an auxiliary layer deposited on a verticalmaterial edge as a spacer, whose layer thickness determines the width ofthe gate base, but, furthermore, also uses said spacer as a positioningmask for the gate head, which is significantly wider than the gate base.On the one hand, it is thus possible to use exclusively opticallithography, and, on the other hand, the self-alignment of gate head andgate base precludes alignment errors as in a plurality of lithographysteps. The gate length is essentially defined by the thickness of theauxiliary layer of the spacer, the steepness of the material edge andthe anisotropy and homogeneity of the spacer etching. However, thesequantities can be set and controlled sufficiently precisely by means ofknown methods, and in particular when using dry-chemical processes.

Preferably, the spacer is produced up to a height above thesemiconductor material which lies above the height of the gate head tobe fabricated. In particular, provision may be made for producing amaterial layer—referred to hereinafter as head layer—on both sidesaround the spacer, a structure for the fabrication of the gate headsubsequently being produced in said layer. The tip of the spacerpreferably projects above said head layer. The head layer may becomposed of a photoresist, for example, and is preferably planarized.

Further layers may be deposited above the spacer, in particular abovethe head layer with the spacer tip projecting thereabove. In particular,a contour layer following the contour of the spacer and the spacer tipmay be provided, which projects through a covering layer deposited aboveit in the region of the spacer. By means of defined etching of thecontour layer with undercutting of the covering layer, it is possible,in the contour layer, for an opening which is centered with respect tothe spacer and extended with respect thereto to be produced as a maskfor the wider gate head structure. In the head layer, a profile taperingtoward the gate base is advantageously produced for the gate head, whichprofile leads to a laterally upwardly curved underside of the gate headwith low capacitance with respect to source and drain and, inparticular, to a spur-free head profile. Preferably, gate base and gatehead are produced in a single process step, in particular by vapordeposition of gate electrode metal.

In an advantageous manner, before the production of the spacer, thesemiconductor material is coated with a protective layer, for example anitride layer, in which an opening to the semiconductor material isproduced after the resolution of the spacer and which is removed onlyafter the deposition of the gate electrode metal. This protective layerprotects the semiconductor surface from damage in the course of thefabrication of the gate electrode, in particular during the variousetching processes. A recess surrounding the gate base in thesemiconductor material is preferably produced in a last etching stepbefore the deposition of the gate electrode metal, so that theparticularly critical semiconductor surface of the recess bottom is notexposed to possibly damaging influences of other process steps. Theseprotective measures are also advantageous with a different procedure forfabricating a gate electrode.

The invention is also illustrated thoroughly below using a preferredexemplary embodiment with reference to the illustrations of FIG. 1a toFIG. 1r, which show a particularly advantageous process sequence forfabricating a PHEMT in a compound semiconductor material.

The invention is explained in more detail below using an exemplaryembodiment with reference to diagrammatic drawings in the figures, inwhich

FIGS. 1a-1 r show process steps for fabricating a PHEMT with aself-aligned T gate.

Proceeding from the GaAs substrate 1, the epitaxially produced layers2-5 define the vertical profile of the transistor, which is coordinatedwith the respective application in the individual case in terms of itsthickness and element structure. Typically, 2 represents the buffer, 3forms the two-dimensional electron gas (the channel), 4 is a stop layerwhich contributes to the defined etching of the recess trench, and 5 isthe highly doped contact layer (FIG. 1a). After the definition of theohmic contacts 6 for source and drain in FIG. 1b, a nitride (Si₃N₄)layer 7 is deposited by PECVD as protective layer and a metallic stoplayer 8 is applied (see FIG. 1c). Afterward, the thermostable resistlayer 9 (e.g. PMGI, PMMA or polyimide) and the inorganic layer 10 areapplied, into which the structure 10 b is transferred through thephotoresist mask 11 b by means of reactive ion etching (RIE). The mask10 b then masks a dry-chemical plasma etching of the thermostable resistlayer 9 and thus defines the structure 9 b, with the material step,which is distinguished by a high sidewall steepness and has no resistbase at the transition to the stop layer 8 (see FIGS. 1d and e). Bothproperties can be produced by setting the parameters of the RIE etchingused, in a manner known per se. After the removal of the mask 10 b, theoxide layer 12 a is deposited by PECVD, which oxide layer forms a spacer12 b on the resist edge as a result of the subsequent anisotropicetching. Depending on the topography of the ohmic contacts 6, it ispossible for further parasitic spacers 12 c to arise (FIGS. 1f and g).After the removal of the thermostable resist layer 9, depending on thechemical composition e.g. in the oxygen plasma or in a wet-chemicalmanner (FIG. 1h), the regions 13 in which the oxide spacer 12 b is to bepreserved are protected by means of a photo-step. The feature size andthe alignment 13 with respect to 12 b are very noncritical. Theparasitic oxide spacers 12 c and also the stop layer 8 not covered by 13are removed (FIG. 1i).

A further resist layer 14 planarizes the surface in such a way that,after a homogeneous dry-chemical resist thinning process, theetched-back resist layer 14 b uncovers the upper part of the spacer 14 b(FIG. 1j). This process step is repeated with a thinner resist ascovering layer 16 after the deposition of an inorganic layer 15, whichfollows the contour of the spacer 14 b, so that the contour layer 15 isvisible above the covering layer only at the spacer 14 b (FIG. 1k).Prior to the thinning process, a structure (not depicted) for a gatecontact region may additionally be exposed in 16. The inorganic layer 15is etched in a manner masked by the etched-back photoresist 16 b andselectively with respect to the oxide layer 12. In this case, theselectivity with respect to the photoresist is chosen to be sufficientlyhigh and the dry-chemical etching has a high isotropic proportion. Adefined undercutting can be achieved as a result. The resultingstructure 15 b of the contour layer, together with the opening 17,determines the size of the gate head (FIG. 1k). Wet-chemical removal ofthe oxide spacer 12 b and the stop layer 8 produces the hole 18, which,together with 16 b, masks the subsequent plasma etching of theprotective layer 7 (FIGS. 1m and n). The resulting hole 19 in theprotective layer 7 subsequently masks the wet-chemical etching of therecess.

A further dry-chemical etching of the head layer with the opening 17 inthe contour layer 15 b as mask 14 b produces a well profile 20, which,on the one hand has a significant undercut with respect to 15 b and, onthe other hand, still covers large parts of te bottom above theprotective layer 7 (FIG. 1o). This form makes it possible to ensure asubsequent gate lift-off is good and the otherwise typical run-outprofile of the lower area of the gate head is avoided during the vapordeposition. The etching of the recess trench 21 (FIG. 1p) is followed bythe gate vapor deposition 22 a, 22 b, 22 c (FIG. 1q).

In this case, 22 a represents the gate base and 22 b represents the gatehead. In the subsequent lift-off process, the photoresist 14 c isremoved wet-chemically and lifts off the layers 15 b and 22 c in theprocess. After the removal of the nitride protective layer 7, thetransistor is passivated with a passivation layer 23, e.g. an Si₃N₄layer, and contact-connected with passive components by means of furthersteps in a customary manner.

The invention is particularly advantageous for field-effect transistorsin compound semiconductor materials in particular in pseudomorphic ormetamorphic III-V HEMT technology, where the gate length and the widthof the recess trench are geometrically particularly critical lateralquantities of less than 0.2 μm, whereas the remaining lateral dimensionsare significantly larger and less critical.

The features which are specified above and those specified in the claimsand also those which can be gathered from the drawings can be realizedadvantageously both individually and in different combinations. Theinvention is not restricted to the exemplary embodiments described, butrather can be modified in various ways within the scope of expertability.

What is claimed is:
 1. A method for fabricating a semiconductorcomponent having a metallic contact electrode that is T-shaped in crosssection comprising the steps of: (a) depositing an auxiliary layer as aspacer on a material edge of a semiconductor material for determiningposition and width of an electrode base; (b) depositing a head layeraround the spacer so that a tip of the spacer projects above the headlayer; (c) using the spacer as a positioning marker for a widerelectrode head; and (d) producing a structure in the head layer forfabricating the electrode head.
 2. The method according to claim 1wherein the semiconductor component is a field-effect transistor with aT gate.
 3. The method according to claim 1, wherein, before theproduction of the spacer, a protective layer is deposited on thesemiconductor material.
 4. The method according to claim 1, wherein acontour layer is deposited on the head layer and the spacer tip and acovering layer is deposited on said contour layer and the contour layeris uncovered above the spacer layer by partial removal of the coveringlayer.
 5. The method according to claim 4, wherein, by undercuttingunder the covering layer, in the contour layer, an extended opening isuncovered around the spacer as mask for the fabrication of the electrodehead.
 6. The method according to claim 1, wherein a profile taperingdownward to the electrode base is uncovered in the head layer.
 7. Themethod according to claim 1, wherein, after the removal of the spacer, arecess trench is etched into the semiconductor material.
 8. The methodaccording to claim 7, wherein the etching of the recess trench isperformed as a last etching step before the deposition of the electrodebase metal (22 a).
 9. The method according to claim 1, wherein theelectrode base and the electrode head are fabricated in one method stepby vapor deposition of an electrode metal.